A study of SAR ADC and implementation of 10-bit asynchronous design
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Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC’s analog components – comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 µm. Design’s noise and power are presented as a breakdown among components.
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Design Techniques for High-Performance SAR A/D Converters
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The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology.
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Implementation of High Speed SAR ADC with Proposed Efficient DAC Architecture
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Electrical and Computer Engineering
A novel, high performance SAR ADC architecture is designed and fabricated in 130nm SiGe technology and 45nm soi technology. In the beginning fundamentals of ADC (Analog-to-Digital Convertor) are introduced and several types of ADC are studied, followed by concepts and details of SAR ADC (Successive Approximation ADC), which consists of sample and hold component, DAC, analog comparator, and SAR logic component. In this paper, the architectures and design details of DAC will be focused, while the design flow and details of other components will be briefly mentioned. The DAC architectures aiming at high speed switching, low power consumption, and minimized mismatch are proposed and fabricated into the whole ADC system. After that the measurements of the 1st fabrication version is presented and analyzed.
http://hdl.handle.net/10415/5901
Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications
- Published: 13 August 2024
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- Zahra Mehrabi Moghadam 1 ,
- Mohammad Reza Salehi 1 ,
- Salman Roudgar Nashta 1 &
- Ebrahim Abiri 1
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This paper presents an ultra-low power comparator with minimum delay and low offset, used in successive approximation register analog-to-digital converters (SAR ADCs) for biomedical system-on-chips (SoCs). To reduce the power consumption, the proposed comparator is designed with a minimum supply voltage in the sub-threshold region. Additionally, intermediate switches are utilized in the design to serve two purposes: 1) breaking the connection between the latch and preamplifier parts during the pre-charge phase to reduce power consumption, 2) reducing the parasitic resistance of the discharge path during the evaluation phase to enhance effective transconductance of the latch ( \({g}_{meff,latch}\) ). Furthermore, the proposed design incorporates, two transistors as auxiliary paths to increase the speed of discharging in the latching process. Overall, the proposed design aims to achieve a low power and high-performance comparator simulated at a frequency of 50 kHz using TSMC 65nm CMOS technology. The post-layout simulation results show that the proposed structure enjoyed from an ultra-low power consumption of 141.4 pW as well as excellent delay and offset with 357 ns and 3.32 mV values, respectively. The occupied area of the designed layout for the proposed comparator is 106.8 μm 2 allowed us to embed it in multi-channel recording system on chips (SoCs). The Figure of Merit (FoM) of the proposed comparator is 0.000463 fVW/Hz. Moreover, the proposed comparator has been validated by using it in successive approximation conversion algorithm with a sampling frequency of 1 kS/s.
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S. Babayan-Mashhadi, R. Lotfi, Analysis and design of a low-voltage low-power double-tail comparator. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22 (2), 343–352 (2014). https://doi.org/10.1109/TVLSI.2013.2241799
Article Google Scholar
P. Bahmanyar, M. Maymandi-Nejad, S. Hosseini-Khayat, M. Berekovic, Design and analysis of an ultra-low-power double-tail latched comparator for biomedical applications. Analog Integr. Circ. Sig. Process 86 , 159–169 (2016)
G. De La Fuente-Cortes, G. Espinosa Flores-Verdad, V.R. Gonzalez-Diaz, A. Diaz-Mendez, A new CMOS comparator robust to process and temperature variations for SAR ADC converters. Analog Integr. Circ. Signal Process. 90 , 301–308 (2017)
A.K. Dubey, R. Nagaria, Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: a low-power, high-speed design approach using bulk-driven load. Microelectron. J. 78 , 1–10 (2018)
J.K. Folla, M.L. Crespo, E.T. Wembe, M.A. Bhuiyan, A. Cicuttin, B.Z. Essimbi, M.B. Reaz, A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage. IET Circuits Devices Syst. 15 (1), 65–77 (2021)
B. Ghanavati, E. Abiri, A. Keyhani, M. Salehi, A. Sanyal, An energy efficient SAR ADC with lowest total switching energy consumption. Analog Integr. Circ. Sig. Process 97 , 123–133 (2018)
P. Ghoshal, C. Dey, S.K. Sen, A 4 bit highly energy and area efficient SC SAR ADC based on a combinational technique with reduced reset energy. Microsyst. Technol. 26 , 1395–1404 (2020)
A. Gupta, A. Singh, A. Agarwal, A low-power high-resolution dynamic voltage comparator with input signal dependent power down technique. AEU-Int. J. Electron. Commun. 134 , 153682 (2021)
M. Hassanpourghadi, M. Zamani, M. Sharifkhani, A low-power low-offset dynamic comparator for analog to digital converters. Microelectron. J. 45 (2), 256–262 (2014)
J. He, S. Zhan, D. Chen, R.L. Geiger, Analyses of static and dynamic random offset voltages in dynamic comparators. IEEE Trans. Circuits Syst. I Regul. Pap. 56 (5), 911–919 (2009)
Article MathSciNet Google Scholar
H.C. Hong, L.Y. Lin, Y. Chiu, Design of a 0.20–0.25-V, sub-nW, rail-to-rail, 10-bit SAR ADC for self-sustainable IoT applications. IEEE Trans. Circuits Syst. Regul. Pap. 66 (5), 1840–1852 (2018)
Y. Hu, C. Chen, Q. Huang, L. Hu, B. Tang, M. Hu, B. Yuan, Z. Wu, B. Li, A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications. Micromachines. 15 (1), 60 (2023)
W. Jendernalik, An ultra-low-energy analog comparator for A/D converters in CMOS image sensors. Circuits Syst. Signal Process. 36 (12), 4829–4843 (2017)
A. Joshi, H. Shrimali, S.K. Sharma, Digitally assisted secondary switch-and-compare technique for a SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 68 (7), 2317–2321 (2021)
Google Scholar
M. Karamimanesh, E. Abiri, K. Hassanli, M.R. Salehi, A. Darabi, A write bit-line free sub-threshold SRAM cell with fully half-select free feature and high reliability for ultra-low power applications. AEU-Int. J. Electron. Commun. 145 , 154075 (2022)
A. Khorami, R. Saeidi, M. Sachdev, M. Sharifkhani, A low-power dynamic comparator for low-offset applications. Integration 69 , 23–30 (2019)
A. Khorami, M. Sharifkhani, High-speed low-power comparator for analog to digital converters. AEU-Int. J. Electron. Commun. 70 (7), 886–894 (2016)
A. Khorami, M. Sharifkhani, Excess power elimination in high-resolution dynamic comparators. Microelectron. J. 64 , 45–52 (2017)
A. Khorami, M. Sharifkhani, A low-power technique for high-resolution dynamic comparators. Int. J. Circuit Theory Appl. 46 (10), 1777–1795 (2018)
B. Lee, H. Kim, J. Kim, K. Han, D.-I.D. Cho, H. Ko, A low-power 33 pJ/conversion-step 12-bit SAR resistance-to-digital converter for microsensors. Microsyst. Technol. 25 , 2093–2098 (2019)
J.Y. Lin, C.C. Hsieh, A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62 (1), 70–79 (2014)
J. Lu, J. Holleman, A low-power high-precision comparator with time-domain bulk-tuned offset cancellation. IEEE Trans. Circuits Syst. I Regul. Pap. 60 (5), 1158–1167 (2013)
S. Nejadhasan, Z. Mehrabi-Moghadam, E. Abiri, M.R. Salehi, Design of a dynamic ADC comparator with low power and low delay time for IoT Application. Wireless Pers. Commun. 123 (2), 1573–1591 (2022)
S. Polineni, M. Bhat, A. Rajan, A 10-Bit differential ultra-low-power SAR ADC with an enhanced MSB capacitor-split switching technique. Arab. J. Sci. Eng. 44 (3), 2345–2353 (2019)
T. Rabuske, F. Rabuske, J. Fernandes, C. Rodrigues, An 8-bit 0.35-V 5.04-fJ/conversion-step SAR ADC with background self-calibration of comparator offset. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (7), 1301–1307 (2014)
G. Raut, A.P. Shah, V. Sharma, G. Rajput, S.K. Vishvakarma, A 2.4-GS/s power-efficient, high-resolution reconfigurable dynamic comparator for ADC architecture. Circuits Syst. Signal Process. 39 (9), 4681–4694 (2020)
B. Razavi, Design of analog CMOS integrated circuits. (2005)
B. Razavi, The StrongARM latch [a circuit for all seasons]. IEEE Solid-State Circuits Mag. 7 (2), 12–17 (2015)
B. Razavi, B.A. Wooley, Design techniques for high-speed, high-resolution comparators. IEEE J. Solid-State Circuits 27 (12), 1916–1926 (1992)
V. Savani, N. Devashrayee, Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator. Microelectron. J. 74 , 116–126 (2018)
N. Shahpari, M. Habibi, P. Malcovati, An early shutdown circuit for power reduction in high-precision dynamic comparators. AEU-Int. J. Electron. Commun. 118 , 153144 (2020)
M. Vafaei, M. Hosseini, E. Abiri, M. Salehi, A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications. Integration 88 , 362–370 (2023)
X. Xin, J.P. Cai, T.T. Chen, Q. Di Yang, A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip. Microelectron. J. 83 , 104–116 (2019)
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Moghadam, Z.M., Salehi, M.R., Nashta, S.R. et al. Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications. Circuits Syst Signal Process (2024). https://doi.org/10.1007/s00034-024-02818-8
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Received : 11 March 2024
Revised : 31 July 2024
Accepted : 02 August 2024
Published : 13 August 2024
DOI : https://doi.org/10.1007/s00034-024-02818-8
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This chapter presents history, economic statistics, and federal government directories of Kemerovo Oblast. Kemerovo Oblast, known as the Kuzbass, is situated in southern central Russia. Krasnoyarsk Krai and Khakasiya lie to the east, Tomsk Oblast to the north, Novosibirsk Oblast to the west, and Altai Krai and the Republic of Altai to the south-west. Kemerovo was founded in 1918 and became the administrative centre of the Oblast upon its formation on 26 January 1943. The city is at the centre of Russia's principal coal mining area. In 2015 Kemerovo Oblast's gross regional product (GRP) amounted to 842,619m. roubles, equivalent to 309,637 roubles per head. The Oblast's main industrial centres are at Kemerovo, Novokuznetsk, Prokopyevsk, Kiselyovsk and Leninsk-Kuznetskii. Kemerovo Oblast's agriculture consists mainly of potato and grain production, animal husbandry and beekeeping. The sector employed 3.6% of the workforce and contributed 4.0% of GRP in 2015.
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Russia after Kemerovo fire: Tuleyev’s 'brawlers', Putin's expectations and spontaneous support campaigns
Political experts established fiasco of existing local government in Kemerovo Oblast
Almost all news flow on 27 March was concentrated on the consequences of the tragedy in Kemerovo. While a crowd of thousands demanded the authorities to resign and its separate participants heard the vice-governor's accusations of PR out, the head of Kemerovo Oblast finally apologised for what had happened. But not in front of the vengeful crowd but in front of President of Russia Vladimir Putin. Residents of the region, in turn, have finally heard only the label 'brawlers'. Realnoe Vremya tells the details with political experts' forecasts about further development of the situation.
''Young man, do you want to hype on the grief?''
The morning in Kemerovo started with a spontaneous demonstration of thousands of locals who demanded to investigate the causes of the fire in Winter Cherry Trade and Leisure Centre, resignation of the regional government together with Governor of Kemerovo Oblast Aman Tuleyev. In brief, the people's demands came to two slogans: ''Truth!'' and ''Away!'' Vice-Governor of Kuzbass Sergey Tsivilyov and First Deputy Governor Vladimir Chernov appeared to reply in front of the deads' relatives, the victims and people simply interested in the misfortune.
People who gathered there spoke about what concerned them into the microphone and ''talked'' with Tsivilyov. So the vice-governor who was expected to occupy the post of the governor of Kemerovo Oblast tried to take the microphone away from a man with a broken heart by accompanying his actions with a question: ''Young man, do you want to hype on the grief?'' Here it became known that young man Igor Vostrikov's sister, wife and three little kids – aged seven, five and two – died in the fire. Later Tsivilyov apologised to the people.
''I apologise once again to those who are in this complicated situation. And I kneel in front of these people,'' the vice-governor addressed the people and really kneeled. The crowd immediately shouted: ''Shame!'' and ''No Need!'', but at the end, some part of people welcomed Tsivilyov's actions with applause.
Vice-Governor of Kuzbass Sergey Tsivilyov appeared to reply in front of the dead's relatives, the victims and people simply interested in the misfortune. Photo: Aleksandra Kryazheva (sputniknews.kz)
Inappropriate prank and morgue raid
People in the demonstration from time to time asked to announce real data on the dead – on 26 March, information that about 300-400 people died in the fire and authorities diligently hid it started to spread in social networks. In answer to it, Sergey Tsivilyov told that relatives said 64 people were missing. Earlier the Investigative Committee denied the information about hundreds of victims. During the demonstration, the very residents made a list which all people could include the names of missing relatives and acquaintances in.
Mayor of Kemerovo Ilya Seredyuk, in turn, gathered ambitious residents who were ready to go through local morgues and go to the fire scene to personally make sure that the information about hundreds of dead people didn't correspond to reality.
In the end, the media claimed Ukrainian phone prank Evgeny Volnov was responsible for distributing the fake information who had posted a recording of the call to Kemerovo's morgue on behalf of an emergency ministry employee on his YouTube channel. It's heard in the recording how he asks how many seats left in the morgue and was indignant that, actually, 300 people died in the fire. According to newspapers, he not only played the ''trick'' but also sent unfamiliar people to collect the flowers and toys the mourners had left on behalf of the presidential administration.
Aman Tuleyev hasn't appeared in front of the residents but was present at the meeting with President of Russia Vladimir Putin. Photo: kremlin.ru
Accusations instead of apologies
Very Governor of the region Aman Tuleyev hasn't appeared in front of the residents but was present at the meeting with President of Russia Vladimir Putin who landed in Kemerovo on 27 March morning. Laying flowers to the memorial to the dead in the fire near the shopping centre, the president visited a hospital with victims and gathered Minister of Emergency Vladimir Puchkov, Minister of Health Veronika Skvortsova, Chairman of the Investigative Committee Aleksandr Bastrykin, Plenipotentiary Ambassador of Russia to Siberian Federal District Sergey Menyailo and very Aman Tuleyev.
At the meeting, the governor apologised for the first time for what had happened. But not to the people but the president.
''Mr Putin, you personally called me. Many thanks again. I personally apologise for what had happened on our territory. But when I reported you, I said 27 people were missing. Then it started to snowball,'' Tuleyev addressed the president of the country.
We need to notice that the word ''brawlers'' was deleted in the version of the transcript that was published on the site of the government – it is how the governor characterised the mourners who were in the demonstration.
''There are about 200 people there today. It's not relatives of the dead, it's those who brawl,'' it's how Tuleyev explained the president the people's discontent by announcing them oppositional force.
By the way, meanwhile, residents were demanding to meet with Vladimir Putin in person in the Freedom Square.
Putin met with citizens in the building of the forensic laboratory, and here he had not the easiest talk with residents of Kemerovo. Citizens demanded the resignation of Governor Tuleyev and thanked for support.
Worldwide mourning
Meanwhile, mourning for the dead in the fire started to be both officially and inofficially declared in other cities across Russia. Later Vladimir Putin signed an official decree declaring 28 March all-Russian mourning day.
Russians also have begun to hold spontaneous memorial services since 26 March. According to Meduza, the school in Beslan, at which 186 kids died in 2004, wrote ''Kemerovo. We Grieve'' the next day after the fire. Memorial services also appeared in other Russian cities and abroad on 27 March. People brought flowers and toys in Magadan, Moscow, Saint Petersburg, Khabarovsk, Ekaterinburg, Belogorsk, Yakutsk, Irkutsk, Kursk… the list is constantly updated. Kazan paid tribute to the memory of the dead near the fountain in Lenin Garden and in the city centre, near Trust sculpture consisting of the figures of a girl, boy and dog. Two pieces of paper were placed there. One of them says: ''Kids, forgive us!'', the other: ''Kemerovo, we're with you!''
Now citizens of Kazan spontaneously gather on Baumana street. People kindle candles, brought flowers.
Sympathising people bring flowers to Russian embassies and consulates abroad. Prague, Erevan, Odessa, Tel Aviv and other are among them.
Channel One employees ran a solidarity campaign and shot a video with a poster #Kemerovowearewithyou.
''Tsivilyov has thrown himself onto a pillbox today. But he didn't hit the pillbox''
Realnoe Vremya asked political experts to assess the current situation in the region and forecast further development of events. Director of Political Expert Group Konstantin Kalachev thinks the existing system of the power vertical under Tuleyev ''turned out to be rotten inside''.
Vice-Governor of Kuzbass Sergey Tsivilyov has been repeatedly called to be one of the main candidates to substitute Aman Tuleyev. Konstantin Kalachev notices that today he has ''buried'' himself as a public politician during the demonstration.
''Director General of Kolmar Trivilyov was supposed to substitute Tuleyev. This is why he has thrown himself onto a pillbox today. But he didn't hit the pillbox. Figuratively speaking, even standing on the knees with a candle won't probably cross out the fact that he didn't learn to speak the same language with the people. And, in fact, he wasn't welcomed with affection,'' says the expert.
He says Tsivilyov's accusation that Igor Vostrikov hyped is a serious mistake.
''It's a serious mistake. In general, if he had handled today's situation, he would have been the next governor. Now it's not so clear,'' supposes Kalachev. In the political expert's opinion, the mayor of Kemerovo also expects resignation after the tragedy.
Director of the Regional Politics Development Centre Ilya Graschenkov also forecasts Ilya Serdyuk's departure. But he adds that the mayor of Kemerovo is the only functionary who speaks the same language with the residents. However, the population's loyalty may not save him from the departure, the newspaper's interlocutor supposes.
From the expert's point of view, the story of Tuleyev's resignation was solved but has been lasting for too long because the current governor promoted his heir, while Moscow – did its own one. Now, after the tragedy, when the fact that Tuleyev doesn't fulfil his obligations became obvious, the political expert believes a new governor will be appointed in several months only – to show the decision was made under public pressure.
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Realnoe Vremya is an online newspaper, providing business news and sectoral analytics, up-to-date information about the development of economy and technology in Tatarstan, Russia and the whole world. Every day Realnoe Vremya’s Editorial board prepares materials and interviews with the leaders of different sectors and markets on the most relevant topics.
IMAGES
COMMENTS
AR ADC was designed and fabricated as a proof of concept for these design techniques.Finally, we investigated the concept of SAR-pipelining as a viable option to realize moderate. o high resolution (> 65 dB SNDR), high-speed (> 150 MS/s), low energy A/D converters. A mod.
One such design idea is explored in this thesis. The goal is to design a high-speed low-power SAR ADC with ENOB > 10 bits in 40 nm CMOS technology. DAC S/H Register Input Digital Output Figure 1.1: Typical SAR ADC. 1.2 Literature Survey The processing speed of SAR ADC can be improved by resolving multiple bits per cycle [3],[4].
This work presents a dual-residue pipelined successive approximation register (SAR) A/D. converter (ADC) architecture that relaxes the accuracy requirement for residue amplifications to. fully utilize the benefits of power efficiency and technology scalability based on zero-crossing. (ZX) only signals.
the comparator reset time, this thesis presents an 8-bit SAR ADC using multiple concurrent comparators. Because each comparator is activated before the previous one is reset completely, the conversion speed. is improved. The proposed design is implemented in 65nm CMOS technology and achieves an SNDR of.
This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register ...
This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC's analog components - comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 µm.
The dual-residue architecture is illustrated with design of an 11b two-step pipelined ADC consisting of 8b coarse and 5b fine (with 2b over-range) SAR sub-ADCs, which resolve 2b and 1b per SAR conversion cycle, respectively. Two ZX signals (or dual-residues) in opposite polarities automatically available in each 2b SAR cycle are sampled and ...
First, a 9-bit 16-way time-interleaved SAR ADC core including decoupling capacitor and voltage references are fully generated by the generator. It works at sampling rate 10GS/s and simulated SNDR is 37.6 dB at Nyquist frequency. In order to set the con guration bits and read out quantized result.
Leading up to this work, a SAR pipeline ADC was modeled in MATLAB as part of a spe-cialization project [5]. The goal of the specialization thesis was to gain an understanding of the operation of the SAR-assisted pipeline ADC, and study how the resolution of the sub-ADCs affect the power consumption in a 15b ADC consisting of a two stage pipeline.
the targeted application. This thesis will give you the opportunity to work on a 6GS/s 10bit TI SAR ADC system in 28nm CMOS. You will improve an already existing ADC Design with adjustments to several components (e.g. the output buffer). This includes schematic design and simulations as well as the following layout and verification steps. Goals:
A 12-bit 400 kSps Successive Approximation Register (SAR) Analog-to-Digital Con-verter (ADC) has been successfully designed and implemented. Pre-layout simulations show that the design consumes 365 μW while achieving SNDR values of 72.07 dB for a 200 MHz input frequency, which corresponds to an ENOB of 11.67 bits.
ous SAR ADC.SAR ADCs, especially when SNDR is lower than 80dB. This boom of SAR ADC is attributed not only to evolution of the improved process technologies bu. also to the innovations in circuit techniques and architectures. In this paper, we will study how SAR ADCs have been evolved by reviewing various design techniques and architectures that.
Also, unlike pipeline ADCs, SAR ADCs do not require an amplifier and are thus better suited for smaller process devices with intrinsically lower gain. For this reason, the group decided to use the SAR architecture for its 65nm ADC. This thesis describes the design port of a comparator for a SAR ADC in digital still
After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously.
Thesis Haoyi Zhao .pdf (1.558Mb) Date 2017-07-27 ... Metadata Show full item record. Abstract. A novel, high performance SAR ADC architecture is designed and fabricated in 130nm SiGe technology and 45nm soi technology. ... and SAR logic component. In this paper, the architectures and design details of DAC will be focused, while the design flow ...
times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements. The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply.
approximation register (SAR) ADC. This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13µm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator.
3.5 SAR ADC waveforms for a scenario that results in a sparkle-code 32 3.6 ADC input vs. normalized total regeneration time for a 6-bit asynchronous SAR ADC with 400mV input swing and 1.05V supply 34 3.7 Estimated sparkle-code error-rate vs. normalized additional conversion time for a 6-bit asynchronous SAR ADC with 400mV input swing and 1.05V ...
This paper presents an ultra-low power comparator with minimum delay and low offset, used in successive approximation register analog-to-digital converters (SAR ADCs) for biomedical system-on-chips (SoCs). To reduce the power consumption, the proposed comparator is designed with a minimum supply voltage in the sub-threshold region. Additionally, intermediate switches are utilized in the design ...
The research also presents a 52Gb/s ADC-based PAM-4 receiver prototype employing. leav. d, 2-bit/stage, 6-bit SAR ADC and a DSP with a 12-tap FFE and a 2-tapDFE. A new DFE architecture that reduces the complexity of a PAM-4 DFE to that of an NRZ DFE while si. ult.
This chapter presents history, economic statistics, and federal government directories of Kemerovo Oblast. Kemerovo Oblast, known as the Kuzbass, is situated in southern central Russia.
Kemerovo Oblast (Russian: Ке́меровская о́бласть, Kemerovskaya oblast), also known as Kuzbass (Кузба́сс) after the Kuznetsk Basin, is a federal subject of Russia (an oblast), located in southwestern Siberia, where the West Siberian Plain meets the South Siberian mountains.The oblast, which covers an area of 95,500 square kilometers (36,900 sq mi), shares a border ...
240 metres (787 feet) Open Location Code. 9M885JRP+VV
Almost all news flow on 27 March was concentrated on the consequences of the tragedy in Kemerovo. While a crowd of thousands demanded the authorities to resign and its separate participants heard the vice-governor's accusations of PR out, the head of Kemerovo Oblast finally apologised for what had happened.